Design Verification Engineer
AdoreSys
Posted
3 weeks ago
Bayan Lepas, Penang, Malaysia
Onsite
MYR 5K
Entry Level
Full Time
Sema Summary
The Design Verification Engineer will develop testbench components and automate validation environments. Candidates should have knowledge in programming and verification methodologies.
About Company
AdoreSys is a semiconductor manufacturing company specializing in ASIC solutions for AI HPC, Automotive ADAS, and Chiplet technologies.
Core Requirements
- Knowledge in C, Python, and shell scripting
- Experience with OVM/UVM validation methodology
- Familiarity with Verilog/System Verilog
- Strong interpersonal and communication skills
- Ability to work in a team and solve problems
Responsibilities
- Develop testbench components using object-oriented programming techniques
- Automate validation environment activities
- Define detailed test plans from specifications
- Write and debug tests in UVM/C++
- Incorporate coverage and assertions for verification completeness
- Collaborate with architects and design engineers
- Ensure 100% verification completeness prior to tapeout
Must Have skills
Job Keywords
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